The present invention relates generally to memory circuits, and, more particularly, to a transistor body bias control circuit for read-only memory (ROM) cells.
A semiconductor memory circuit stores data electronically. One type of memory circuit is a ROM, which is made up of an array of ROM cells. A ROM cell typically includes a set of transistors that have threshold voltages that determine a read margin (i.e., accuracy of a read operation) of the ROM cell. However, as semiconductor device sizes shrink, fluctuations in the threshold voltages increase due to random dopant fluctuation (RDF), line edge roughness (LER), and short channel effects (SCE). Further, at low operating voltages (e.g., 0.8 volts at 40 nanometer technology node), there is an additional increase in threshold voltage fluctuations. These fluctuations degrade the read margin.
The read margin of the ROM cell is further dependent on temperature, as the threshold voltage varies with temperature. For example, threshold voltages are higher at low temperatures as compared to high temperatures, so the read margin degrades at low temperatures as compared to high temperatures. Further, the higher threshold voltages at low temperatures degrade a read current of the ROM cell, especially at the low operating voltages. The degradation in the read current results in degradation in the speed of the ROM cell.
A conventional approach to reduce the read margin and operational speed degradations of the ROM cell is to reduce the threshold voltages at low temperatures. However, reduction in the threshold voltages at low temperatures reduces the threshold voltages at high temperatures, which in turn increases static leakage power of the ROM cell at high temperatures. To solve this problem, biasing techniques are used to bias the transistors in the ROM cells. The biasing techniques may be implemented with biasing circuits that include various combinations of transistors, resistors, diodes, and the like, and include generating a bias voltage that is provided to body terminals of the ROM cell transistors to control the corresponding threshold voltages. However, employing the biasing circuits consumes additional area and power. Further, the additional power increases the static leakage power.
Therefore, it would be advantageous to have a biasing technique that maintains the read margin of a ROM cell above an acceptable level over a temperature range, increases an operational speed of the ROM cell, and solves the above-mentioned problems of the conventional approaches of reducing the read margin and operational speed degradation.